1. Field of the Invention
This invention relates in general to electronic devices and specifically to charge pumps.
2. Description of the Related Art
Phase locked loops (PLL) are utilized by electronic devices to generate clock signals from a reference signal. The generated clock signal maybe at the same frequency as the reference clock signal or at a fractional or multiple frequency of the reference clock signal. The generated clock signal typically has a predetermined phase relationship with the reference clock signal.
Typically, a PLL utilizes a charge pump which receives clock control signals from a phase frequency detector (PFD) and provides current to a filter capacitor to control the voltage of a frequency control input of a voltage controlled oscillator (VCO).
With PLLs implemented in semiconductor devices, the filter capacitor may be constructed by utilizing CMOS technology. The drive to reduce the size of electronic devices has increased the difficulty of implementing filter capacitors in a semiconductor device. For example, reducing the thickness of gate oxides increases the gate leakage currents of a capacitor implemented in a semiconductor device. Also, reducing the size of semiconductor devices means that a proportionally larger area of the device must be allocated to obtain the same capacitance.
In addition, conventional charge pumps typically require high tolerance transistors and resistors to ensure reliable operation. As the size of semiconductor devices decreases, providing high tolerance transistors, resistors, and diodes becomes more difficult. What in needed is an improved charge pump for electronic circuits such as phase locked loops.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted.